The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device performing a data masking operation by receiving a data masking signal through a pad, wherein an address signal is inputted through the pad.
Nowadays, various electronic instruments are being developed into satisfying needs for a high speed operation, miniaturization, low power consumption and low price, and thus a semiconductor memory device is also being developed into a direction of achieving the high speed operation, the high integration and the low power consumption. As part of the high speed operation and the low power consumption, there is a data masking operation. Data masking operation means “sorting out data.” Therefore, by masking the progress of some of unnecessary data in a reading or writing operation through the data masking operation, it is possible to prevent undesired current consumption as well as achieve more rapid data input/output, so that the semiconductor memory device can operate at a high speed.
FIG. 1 illustrates a block diagram for explaining a data masking operation in a conventional semiconductor memory device.
As shown, the conventional semiconductor memory device includes a plurality of banks BANK 0, BANK 1, BANK 2, and BANK 3, each of which has a plurality of cells, a plurality of data pads DQ PAD<0:31> for receiving data signals DATA<0:31> having a plurality of bits, a plurality of address pads ADDRESS PAD<0:11> and BANK ADDRESS PAD<0:3> for receiving address signals ADDRESS<0:11> having a plurality of bits and bank address signals BANK ADDRSSS<0:3>, a plurality of data masking pads DM PAD 0, DM PAD 1, DM PAD 2, and DM PAD 3 for receiving a plurality of data masking signals DATA_MSK0, DATA_MSK1, DATA_MSK2, and DATA_MSK3, and an address decoder for decoding the address signals ADDRESS<0:11> and the bank address signals BANK ADDRESS<0:3> inputted through the plurality of address pads ADDRESS PAD<0:11> and BANK ADDRESS PAD<0:3> and transferring the decoded signals to the plurality of banks BANK 0, BANK 1, BANK 2, and BANK 3.
In order to perform the data masking operation, the conventional semiconductor memory device separately includes the plurality of data masking pads DM PAD 0, DM PAD 1, DM PAD 2, and DM PAD 3 and receives the plurality of data masking signals DATA_MSK0, DATA_MSK1, DATA_MSK2, and DATA_MSK3 through the plurality of data masking pads DM PAD 0, DM PAD 1, DM PAD 2, and DM PAD 3. Hereinafter, the operation of receiving the plurality of data masking signals DATA_MSK0, DATA_MSK1, DATA_MSK2, and DATA_MSK3 will be described.
If the data masking operation is not performed, all of the plurality of data masking signals DATA_MSK0, DATA_MSK1, DATA_MSK2, and DATA_MSK3 inputted through the plurality of data masking pads DM PAD 0, DM PAD 1, DM PAD 2, and DM PAD 3 are disabled.
Therefore, the plurality of data signals DATA<0:31> corresponding to the plurality of data pads DQ PAD<0:31> may be freely inputted/outputted to/from cells that are selected from the plurality of cells included in each of the plurality of banks BANK 0, BANK 1, BANK 2, and BANK 3 in response to row address signals ROW ADDRESS<0:11> and column address signals COLUMN ADDRESS<0:6> outputted from the address decoder.
On the other hand, if the data masking operation is performed, the 0th masking signal DATA_MSK0 and the first data masking signal DATA_MSK1 among the plurality of data masking signals DATA_MSK0, DATA_MSK1, DATA_MSK2, and DATA_MSK3 inputted through the plurality of data masking pads DM PAD 0, DM PAD 1, DM PAD 2, and DM PAD 3 may be enabled, whereas the second data masking signal DATA_MSK2 and the third masking signal DATA_MSK3 may be disabled.
Therefore, although a certain cell is selected from the plurality of cells included in each of the banks BANK 0, BANK 1, BANK 2, and BANK 3 in response to the row address signals ROW ADDRESS<0:11> and the column address signals COLUMN ADDRESS<0:6> outputted from the address decoder, the data signals DATA<0:15> cannot be freely inputted/outputted to/from the cells that are selected from the 0th bank BANK 0 and the first bank BANK 1 corresponding to the enabled 0th data masking signal DATA_MSK0 and the enabled first data masking signal DATA_MSK1, respectively, whereas the data signals DATA<16:31> can be freely inputted/outputted to/from the cells that are selected from the second bank BANK 2 and the third bank BANK 3 in response to the disabled second data masking signal DATA_MSK2 and the disabled third data masking signal DATA_MSK3, respectively.
That is, since the 0th to the 15th data signals DATA<0:15> corresponding to the 0th to the 15th data pads DQ PAD<0:15> among the plurality of data pads DQ PAD<0:31> cannot be inputted/outputted by the enabled 0th data masking signal DATA_MSK0 and the enabled first data masking signal DATA_MSK1, the 0th to 15th data signals DATA<0:15> cannot be transferred from the external to the 0th bank BANK 0 and the first bank BANK 1 and the 0th to 15th data signals DATA<0:15> stored in the 0th bank BANK 0 and the first bank BANK 1 cannot be outputted to the external.
Meanwhile, since the 16th to the 31st data signals DATA<16:31> corresponding to the 16th to the 31st data pads DQ PAD<16:31> among the plurality of data pads DQ PAD<0:31> can be inputted/outputted by the disabled second data masking signal DATA_MSK2 and the disabled third data masking signal DATA_MSK3, the 16th to 31st data signals DATA<16:31> can be transferred from the external to the second bank BANK 2 and the third bank BANK 3 and the 16th to 31st data signals DATA<16:31> stored in the second bank BANK 2 and the third bank BANK 3 can be outputted to the external.
As described above, the conventional semiconductor memory device properly adjusts enablement/disablement of the plurality of data masking signals DATA_MSK0, DATA_MSK1, DATA_MSK2, and DATA_MSK3 to sort out data pads to be masked or data pads not to be masked.
For instance, the conventional semiconductor memory device employs a scheme of allowing one data masking signal to mask one byte of data signals, i.e., 8 data signals. In another example, the conventional semiconductor memory device may employ a scheme of allowing one data masking signal to mask data signals whose number is greater or smaller than one byte.
If performing the data masking operation by directly receiving the plurality of data masking signals DATA_MSK0, DATA_MSK1, DATA_MSK2, and DATA_MSK3 from the external such as in the conventional semiconductor device, the data masking operation can be simply performed. However, in that case, there is a problem of necessarily requiring the plurality of data masking pads DM PAD 0, DM PAD 1, DM PAD 2, and DM PAD 3 to receive the plurality of data masking signals DATA_MSK0, DATA_MSK1, DATA_MSK2, and DATA_MSK3 from the external.